To support its research activities, CSIRO develops custom wireless and signal processing systems operating at frequencies up to 110 GHz. The most famous system is the original WiFi test bed, built during the 1990s to demonstrate the practical application of CSIRO’s WiFi research and patents. More recent projects include Gigabit modems, correlators for Radio Astronomy, and other specialised radio and advanced digital signal processing systems.
The team of engineers that develops these systems has skills that cover the wide range of activities required to reduce complex radio and signal processing theory to a system concept that can be effficiently implemented in hardware and software. These skills include:
Laboratory facilities that support this work include:
The pictures below show examples of some devices that have been developed
This modem achieves less than 400 ns latency while transmitting a 10 Gbit/sec data stream with LDPC encoding at E-band frequencies (71-86 GHz). The design includes two 5 Gsample/sec ADCs, four 2.5 Gsample/sec DACs, QSFP Optical Ethernet interface and Virtex 7 FPGA with 1.5M lines of VHDL code implementing the radio algorithms. The PCB is a custom 20-layer design, using low-dielectric substrate for control of transmission line impedances. Modem parameters are monitored via a USB-based interface. PC software and a GUI was developed to configure the modem and monitor its operation. The modem is sold commercially.
This hardware was developed to show the feasibilty of localising WiFi transmissions. The picture above shows custom radio cards (two at bottom), each with 56 MHz bandwidth operating in the 5 GHz WiFi bands with low-noise receive, +10 dBm transmit and self-calibration capability. The radios are designed to be overlapped in frequency so that with three combined the system can receive or produce a 150 MHz bandwidth transmission in a phase-coherent manner. A commercial microZed board (top) runs a custom embedded Linux software application (10k lines of code) and its FPGA is programmed with 5k lines of VHDL code implementing algorithms used to receive and localise WiFi transmissions. The board in the middle of the stack contains battery charging and monitoring circuitry, supervised by a low-power microprocessor that monitors battery charge and sequences system startup.